By Topic

FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
G. Ramirez-Conejo ; Electron. Dept., Tecnological Inst. of Celaya, Celaya Gto, Mexico ; J. Diaz-Carmona ; A. Ramirez-Agundis ; A. Padilla-Medina
more authors

This paper describes a reconfigurable hardware implementation for wideband fractional delay FIR filters. The proposed implementation is based on a multirate Farrow structure, reducing in this way the arithmetic complexity compared to the modified Farrow structure, and allowing on line fractional delay value update. A minimax frequency optimization technique is used for computing the structure coefficients. In order to reduce the resources usage the structure filters multiplications are implemented using distribute arithmetic technique. The resulting filter implementation is tested through software simulation and hardware implementation tools. The filter performance is measured in terms of area, throughput and dynamic power consumption. Accordingly to the obtained results the described structure allows the implementation of wideband fractional delay FIR filters with online factional value update. A fine fractional delay resolution is achieved with the proposed hardware implementation.

Published in:

2010 International Conference on Reconfigurable Computing and FPGAs

Date of Conference:

13-15 Dec. 2010