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Parallel FPGA-Based Implementation of Recursive Sorting Algorithms

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4 Author(s)
Mihhailov, D. ; Comput. Dept., TUT, Tallinn, Estonia ; Sklyarov, V. ; Skliarova, I. ; Sudnitson, A.

The paper describes the hardware implementation and optimization of parallel recursive algorithms that sort data using binary trees. Since recursive calls are not directly supported by hardware description languages, they are implemented using the model of a hierarchical finite state machine (HFSM). Parallel processing is achieved by constructing N binary trees (N>;1) and applying concurrent sorting to N trees at the same time with the aid of N communicating HFSMs. The paper presents new results in: 1) parallel sorting algorithms, 2) FPGA-based parallel architectures, and 3) the analysis and comparison of alternative and competitive techniques for implementing parallel recursive algorithms. Experiments demonstrate that the performance of sorting operations is increased compared to previous implementations.

Published in:

Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on

Date of Conference:

13-15 Dec. 2010