Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA

Power optimization has become one of the most challenging design objectives of modern digital systems. Although FPGAs are more and more used, they are however still considered as power inefficient compared to standard-cell or full-custom technologies. New dedicated design approaches are thus needed to reduce this gap. In this paper, we address low-power design on FPGA through a dedicated High-Level Synthesis (HLS) flow. The proposed approach allows to slow down the clock frequency in parts of the design, decrease the complexity of the clock-network, reduce the number of long wires and perform clock-gating. The design flow has been fully implemented and allows to automatically synthesize hierarchical and synchronous multiple-clock domain architectures. The power consumption of the architectures we generate has been investigated and compared with state-of-the-art synthesis approaches. The experiments have been realized by using a Xilinx Virtex-5 device and the power measurement results show the interest of the proposed approach.