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Test Compression for Dynamically Reconfigurable Processors

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5 Author(s)
Inoue, H. ; NEC Corp. & Renesas Electron., Kawasaki, Japan ; Yamada, J. ; Yoneda, H. ; Togawa, K.
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We present the world's first test compression technique that features automation of compression rules for test time reduction on dynamically reconfigurable processors. Evaluations on an actual 40-nm product show that our technique achieves a 2.7 times compression ratio for original configuration information (better than does GZIP), the peak decompression bandwidth of 1.6 GB/s, and 2.7 times shorter test times.

Published in:

Field Programmable Logic and Applications (FPL), 2010 International Conference on

Date of Conference:

Aug. 31 2010-Sept. 2 2010