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Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs)

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2 Author(s)
Doris Chen ; Univ. of Toronto, Toronto, ON, Canada ; Deshanand Singh

GPUs are becoming an increasingly attractive option for obtaining performance speedups for data-parallel applications. FPGA technology mapping is an algorithm that is heavily data parallel; however, it has many features that make it unattractive to implement on a GPU. The algorithm uses data in irregular ways since it is a graph-based algorithm. In addition, it makes heavy use of constructs like recursion which is not supported by GPU hardware. In this paper, we take a state-of-the-art FPGA technology mapping algorithm within Berkeley's ABC package and attempt to parallelize it on a GPU. We show that runtime gains of 3.1× are achievable while maintaining identical quality as demonstrated by running these netlists through Altera's Quartus II place-and-route tool.

Published in:

2010 International Conference on Field Programmable Logic and Applications

Date of Conference:

Aug. 31 2010-Sept. 2 2010