By Topic

Automatic extraction of higher order interconnect parasitics for device level simulators for VHSIC applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
M. Mokhtari ; Dept. of Electron., R. Inst. of Technol., Kista, Sweden ; T. Juhola ; G. Schuppener ; F. Sellberg

The necessary routines for extraction of interconnect parasitics have been implemented in Cadence DFWII environment. The implementation allows choice of parasitics based on “pure-capacitive”, “RC-” or third order “LRC-” filter. Eye-diagram simulations on CMOS and bipolar gates on Si and HBT gates on InP, emulating MSI Very High Speed circuits, have shown that “LRC”-extraction of the power-lines in the case of CMOS in the GHz region is vital in predicting the circuit behaviour. The bipolar test-bed has shown considerably less sensitivity to power-lines. The signal path is more relevant for LRC-extraction in the latter

Published in:

Analog and Mixed IC Design, 1996., IEEE-CAS Region 8 Workshop on

Date of Conference:

13-14 Sep 1996