An 8-bit 70-MHz CMOS digital-to-analog converter with two-stage current cell matrix structure

This paper describes an 8-bit 70-MHz CMOS digital to analog converter (DAC) with two stage current cell matrix structure which is composed of a 4 MSB current matrix stage and a 4 LSB current matrix stage. The two stage current cell matrix architecture allows the designed DAC to reduce not only the complexity of the decoding logic, but also the number of current sources. Fast settling time and low power consumption of the DAC are achieved by utilizing the proposed architecture. The simulation results show that the maximum conversion rate is 70 MHz, the power dissipation is 24.5 mW with a single power supply of 3.3 V, and the chip size is 0.8 mm/spl times/1.0 mm for a CMOS 1.5 /spl mu/m n-well technology.