By Topic

An 8-bit 70-MHz CMOS digital-to-analog converter with two-stage current cell matrix structure

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ji Hyun Kim ; Dept. of Electron. Eng., Inha Univ., Inchon, South Korea ; Kwang Sub Yoon

This paper describes an 8-bit 70-MHz CMOS digital to analog converter (DAC) with two stage current cell matrix structure which is composed of a 4 MSB current matrix stage and a 4 LSB current matrix stage. The two stage current cell matrix architecture allows the designed DAC to reduce not only the complexity of the decoding logic, but also the number of current sources. Fast settling time and low power consumption of the DAC are achieved by utilizing the proposed architecture. The simulation results show that the maximum conversion rate is 70 MHz, the power dissipation is 24.5 mW with a single power supply of 3.3 V, and the chip size is 0.8 mm×1.0 mm for a CMOS 1.5 μm n-well technology

Published in:

Circuits and Systems, 1996., IEEE Asia Pacific Conference on

Date of Conference:

18-21 Nov 1996