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Pulse-width-modulation feedforward neural network design with on-chip learning

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2 Author(s)
Jenn-Chyou Bor ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chung-Yu Wu

In this paper, a CMOS VLSI design of the pulse width modulation (PWM) neural network with on-chip leaning is proposed. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits with good linearity and large dynamic range. From the measured results, the linearity of synapses versus input pulse widths can be almost kept under ±0.2%. Also the measured results on the simple Chinese word speech classification have successfully verified the function correctness and performance of the designed neural network

Published in:

Circuits and Systems, 1996., IEEE Asia Pacific Conference on

Date of Conference:

18-21 Nov 1996