Array Processors Designed with VHDL for Solution of Linear Equation Systems Implemented in a FPGA

This paper presents a parallel array of processors implemented in a Field Programmable Gate Array (FPGA) for the solution of linear equation systems. The solution is performed using the division-free Gaussian elimination method. This algorithm was implemented in integrated processors in a FPGA Spartan 3 of Xilinx. A top-down design was used. The architecture modules were designed in VHDL language and simulated using the Model Sim 6.3f software. The proposed architecture can handle IEEE 754 single and double precision floating-point data and the architecture is implemented in 240 identical processors. Also, an algorithmic complexity of O(n
²
) was obtained using a n
²
processor scheme that performs the solution of the linear equations.