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Memory Built-in Self Test (MBIST) is the popular approach to test embedded memories. There are two types of MBIST controllers, the state-machine based and the micro code-based where the micro code-based controllers are commonly designed as programmable memory BIST (P-MBIST). Most micro code-based P-MBISTs employ one instruction per MARCH operation. Latest micro code-based PMBIST utilizes only one instruction per MARCH element. This technique certainly decreases the area overhead because the numbers of required instructions are reduced. However, numbers of operations per sequence cause the instruction lengths to be varied. This unfixed microcode's instruction length still results in higher area overhead. To overcome this problem, a new way of micro-coding the test instruction is created. The components of the proposed P-MBIST controller are designed and explained. These controllers are written using Verilog HDL and implemented in ALTERA Cyclone II FPGA. Analysis on the architectures of the proposed P-MBIST and P-MBIST is performed. The simulation and synthesis result of the proposed P-MBIST controller is presented and discussed.