By Topic

An implementation of the 155M physical layer ASIC for ATM network-node interface

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Chung-Wook Suh ; Dept. of Integrated Circuit Res., Electron. & Telecommun. Res. Inst., Taejon, South Korea ; Sung-Do Kim ; Hee-Bum Jung ; Sang-Hoon Choi
more authors

This paper describes an implementation of the 155M physical layer ASIC for ATM network-node interface, which contains transmit synthesizer, receive bit synchronizer, transmission convergence, the microprocessor interface and UTOPIA (Universal test and operation of the PHY interface for ATM). This ASIC fully conforms the recommendations of ITU-T and ATM forum. This chip was implemented in a 0.8 μm double metal, n-well CMOS process. A total of 320,960 transistors were integrated on 9 mm×9.2 mm silicon chip that consumes a maximum of 1.02 W power at 5 V using a 155 MHz clock

Published in:

Circuits and Systems, 1996., IEEE Asia Pacific Conference on

Date of Conference:

18-21 Nov 1996