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A PLL (phase-locked loop)-type 2.4GHz frequency synthesizer is designed in the standard 0.18µm mixed-signal and RF 1P6M CMOS technology of SMIC. It integrates a VCO, a dual-modulus prescaler, PFD, a charge pump, a control logic, various digital counters and digital registers onto a single chip. With the help of the linear model of the loop, the design and optimization of the loop parameters are discussed in detailed. The VCO is implemented in the CMOS technology of SMIC. The measured phase noise is −125.3 dBc/Hz at offset frequency 1 MHz from the carrier of 2.466 GHz while the VCO core circuit draws only 720 µW from a 0.4 V supply. The designed VCO can cover the frequency range from 2.28 to 2.48 GHz. The simulated results of the PLL show that frequency synthesizer can be in the locked-state quickly. The layout area is 0.675 mm×0.750 mm. The DC power consumption of the core part is about 20 mW under 1.8 V supply.