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A gate level sensor network for integrated circuits temperature monitoring

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3 Author(s)
Vahdatpour, A. ; Comput. Sci. Dept., Univ. of California Los Angeles, Los Angeles, CA, USA ; Meguerdichian, S. ; Potkonjak, M.

We present the first sensor network architecture to monitor integrated circuits (IC) thermal and energy activity. The sensor network consists of a set of simple gates, which are superimposed over the actual design of any IC. The sensing network and the actual IC design are completely disjoint in order to enable their simultaneous operation. Since the delay of gates is proportional to their temperature, we can obtain temperature of the network gates, by measuring the delay of the gates in the self-sensing network. Once we measured the delay of the circuit, we use CMOS temperature-delay relation and linear programming formulation to calculate the temperature at any point on the chip. High resolution (spatial and temporal) temperature monitoring allows several run-time optimizations. Protecting shared processors from permanent localized damage through rapid creation of hot spots and efficient accounting of the available energy supply are among two main applications of our IC sensor network.

Published in:

Sensors, 2010 IEEE

Date of Conference:

1-4 Nov. 2010