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A hierarchical optimization methodology is presented to achieve robust analog/mixed-signal circuit design with consideration of process variations. Hierarchical optimization using building circuit block Pareto models is an efficient approach for optimizing nominal performances of large analog circuits. However, yield-aware system optimization, as dictated by the need for safeguarding chip manufacturability in scaled technologies, is completely nontrivial. Two fundamental difficulties are addressed for achieving such a methodology: yield-aware Pareto performance characterization at the building block level and yield-aware optimization problem formulation at the system level. In addition, postsilicon tuning in complex mixed-signal system designs is investigated and the proposed optimization framework is extended for such systems. The presented methodology is demonstrated by hierarchical optimization of a phased-locked loop consisting of multiple building blocks and self-tuning function blocks.