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The implementation of a high precision fractional-N divider, which is one of the components of a phase-locked loop (PLL) fractional-N frequency synthesizer for Digital Audio Broadcasting (DAB) and other modern communication systems, is presented. Unconditionally stable Δ-Σ modulators of the third order (namely MASH-1-1-1) are implemented in the frequency synthesizer and they can provide a good average estimate for the fractional-N dividers. By cooperating with a dual-modulus prescaler, this divider can achieve a fractional frequency division from 509.74 to 703.10 with the precision of 1/224. This divider has been designed in a SMIC 0.18-μm CMOS technology and by using Artisan standard cell library. The chip area is 323 μm × 323 μm. Simulation results show that it works correctly and can realize a frequency division with a high precision.