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Pipelined implementation of AES encryption based on FPGA

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2 Author(s)
Yulin Zhang ; Sch. of Inf. Sci. & Eng., Univ. of Jinan, Jinan, China ; Xinggang Wang

This paper presents the outer-round only pipelined architecture for a FPGA implementation of the AES-128 encryption processor. The proposed design uses the Block RAM storing the S-box values and exploits two kinds of Block RAM. By combining the operations in a single round, we can reduce the critical delay. Therefore, our design can achieve a throughput of 34.7 Gbps at 271.15 Mhz and 2389 CLB Slices with 200 BRAM. We can get the much higher efficiency than any other implementation reported in the literature.

Published in:

Information Theory and Information Security (ICITIS), 2010 IEEE International Conference on

Date of Conference:

17-19 Dec. 2010