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A 700-Mb/s/pin CMOS signaling interface using current integrating receivers

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2 Author(s)
Sidiropoulos, S. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Horowitz, M.

A high speed CMOS signaling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes I-V push-pull drivers, a delay line phase-locked loop (PLL), and sampling of the data on both edges of the clock. In order to increase the noise immunity of the reception, a current-integrating input pin sampler is used to receive the incoming data. Chips fabricated in a 0.8 μm CMOS technology achieve transfer rates of 740 Mb/s/pin operating from a 3.3 V supply with a bit error rate of less than 10-14

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:32 ,  Issue: 5 )

Date of Publication:

May 1997

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