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A 14 b 23 MS/s 48 mW Resetting \Sigma \Delta ADC

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2 Author(s)
Chun C. Lee ; Intel Corporation, Hillsboro, OR, USA ; Michael P. Flynn

High-resolution, moderate-speed, calibration-free analog-to-digital converters (ADCs) are becoming increasingly difficult to design in low-voltage nanometer-scale CMOS processes. We propose an ADC architecture based on a resetting ΣΔ modulator that achieves high resolution, despite poor component matching and poor analog transistor performance. A prototype design pipelines a second-order resetting ΣΔ modulator and a 10 b cyclic ADC. The device achieves 14 b resolution and samples as a Nyquist converter at 23 MS/s. This calibration-free ADC achieves no missing codes, 87 dB SFDR and 11.7 b ENOB. The ADC is fabricated in 0.18 μm CMOS and occupies a core area of 0.5 mm2. It consumes 48 mW from a 2 V supply.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:58 ,  Issue: 6 )