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Preventing boron penetration through 25-/spl Aring/ gate oxides with nitrogen implant in the Si substrates

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4 Author(s)
Liu, C.T. ; AT&T Bell Labs., Murray Hill, NJ, USA ; Ma, Y. ; Luftman, H. ; Hillenius, S.J.

For gate oxides thinner than 40 /spl Aring/, conventional schemes of incorporating N in the oxides might become insufficient in stopping B penetration. By implanting N into the Si substrates with a sacrificial oxide layer; we have grown 25 /spl Aring/ gate oxide and prevented B penetration in the presence of F after 90 min of 850/spl deg/C and 10 s of 1050/spl deg/C anneals. SIMS analyses surprisingly reveal a N peak formed within the thin oxide layer, while no N is left in the Si substrate beyond the oxide layer. In addition, no B is seen in the substrate, either. As a consequence, threshold voltage of pMOSFETs is shifted to a more negative value which agrees with calculations assuming no B penetration. Meanwhile, threshold voltage of nMOSFETs is not affected by the N implant, which confirms that B penetration is the only explanation for the pMOSFET data. Prevention of B penetration also improves the short-channel effects for 0.25-/spl mu/m pMOSFETs, while no difference is seen in nMOSFETs with and without N implant.

Published in:

Electron Device Letters, IEEE  (Volume:18 ,  Issue: 5 )

Date of Publication:

May 1997

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