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Considering recent developments in the field of carry-save representation in synthesis of arithmetic circuits, it was considered imperative to develop an automated system to optimize an arithmetic circuit design to handle cases of practical interest, including scattered logic, and generate an optimized solution in Verilog; so that it could reduce both design and debugging costs drastically. We, therefore, designed, developed and implemented a specialized system using adaptive transformations for automated optimization of data path designs as well as verified and validated results for large set of circuits of varying complexity and number of nodes using Xilinx and ChipScope Pro. The developed system takes circuit design from our specialized drag-and-drop interface, and applies automated arithmetic transformations to reduce the critical path complexity and the cell area with the quality of manual implementations, and generate its hardware implementation ready for synthesizes as high-quality arithmetic circuits. Behavioral simulation of pre and post optimization circuits was monitored in ChipScope Pro to verify our Algorithm, and establish that it preserves the logic. Furthermore, results of synthesis reports generated by Xilinx were compared with those reported by other researchers in recent past and found them to be comparable and in certain cases even better. Our algorithm is independent of compression tree implementation and its performance can further improve with better implementation. We believe this work will enhance efficiency and reduce cost through selection of best circuit design for fabrication.