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This work presents the design of a Low Noise Amplifier in 0.35 μm CMOS technology from Taiwan Semiconductors. A single ended cascade configuration with inductive degeneration followed by a common source configuration is used. The circuit is designed in Cadence and employs feedback technique along with the use of a PMOS as a feed forward distortion canceller to further improve linearity. At 900 MHz, the low noise amplifier has a gain of 10.3 dB, noise figure of 3.2 dB, input referred 1 dB-CP of -2.75 dBm, output referred 1 dB-CP of 6.85 dBm, IIP3 of +11.74 dBm and OIP3 of +21.76 dBm consuming 26 mA from 1.5 V supply. This design has the best input referred 1dB-CP reported till date in 0.35 μm technology for the desired frequency of operation.