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In this paper, we investigate the properties of a submicron pMOS with a single layer of metallization. The fabrication process and electrical characterization of the device were simulated using the SILVACO TCAD tools. We have applied constant field scaling on the effective channel length, the density of ion implantation for threshold voltage adjustment, and gate oxide thickness. To suppress short channel effects, we have also applied retrograde well implantation, Shallow Trench Isolation (STI), sidewall spacer deposition, silicide formation, and Lightly Doped Drain implantation in our process simulation. We have validated the electrical performance of the device by plotting and analyzing the ID-Vg relationship.