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A novel digital signal processing algorithm for online estimation of the fundamental frequency of the distorted power system signals is presented. The basic algorithm relies on the development of an efficient variance reduction algorithm; and design of a new stable bandpass infinite impulse response (IIR) second-degree digital integrator (SDDI) with reduced approximation error. Compared with the well-established technique such as the enhanced-phase-locked-loop (EPLL) system, the proposed algorithm provides the following: 1) higher degree of immunity and insensitivity to harmonics and noise and 2) faster response during step frequency change. Structural simplicity, wide range of application, controls over speed and accuracy, and parameter robustness are other salient features of the method. The only limitation as compared with the EPLL system is its slower transient response during step change in signal magnitude. Based on simulation studies, performances of the proposed algorithm at different operating conditions have been presented, and its accuracy and response time have been compared with the EPLL systems.
Instrumentation and Measurement, IEEE Transactions on (Volume:60 , Issue: 3 )
Date of Publication: March 2011