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Low noise-low power digital phase-locked loop

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3 Author(s)
Saber, M. ; Dept. of Inf., Kyushu Univ., Fukuoka, Japan ; Jitsumatsu, Y. ; Khan, M.T.A.

We propose a phase-locked loop (PLL) architecture, which reduces the double frequency ripple without increasing the order of loop filter. Proposed architecture uses quadrature numerically-controlled oscillator (NCO) to provide two output signals with phase difference of π/2. One of them is subtracted from the input signal before multiplying with the other output of NCO. The system also provides stability in case the input signal has noise in amplitude or phase. The proposed structure is implemented using field programmable gate array (FPGA), which dissipates 15.44 mW and works at clock frequency of 155.8 MHz.

Published in:

TENCON 2010 - 2010 IEEE Region 10 Conference

Date of Conference:

21-24 Nov. 2010

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