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Design techniques for testable embedded error checkers

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1 Author(s)
E. J. McCluskey ; Comput. Syst. Lab., Stanford Univ., CA, USA

Design techniques to ensure the testability of embedded checkers that cannot be tested by scan-path bistables are presented. The discussion covers: types of error detectors; parity checkers and self-testing circuits; two-rail checkers; M-out-of-N checkers; and equality checkers. The techniques outline guarantee single stuck fault testability.<>

Published in:

Computer  (Volume:23 ,  Issue: 7 )