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This study describes the design methodology of optimising the power-added efficiency (PAE) of switching mode power amplifiers (SMPAs). To maximise efficiency, design optimisation of the harmonic loading networks using an analytical analysis approach is proposed. Indeed, by carefully designing a distributed harmonic control network at the output of the SMPA, the insertion loss through the load network can be minimised. To validate the PAE optimisation approach, two 10 W inverse class F power amplifiers (PAs) were designed, manufactured and tested at a frequency of 2.45 GHz using a GaN HEMT transistor. The first PA prototype was matched with a standard distributed harmonic loading network and the second with the proposed distributed harmonic loading network. The measured PAE and gain for the second prototype were improved by 3 and 0.17 dB to reach 73 and 14 dB, respectively.