Referenced Items are not available for this document.
Describes a new hardware architecture known as an edge painting tree (EPT) pipelined binary trees for fast generation of scanline images for raster scan graphics targeted for surface or solid modelling. The hardware complexity of EPT is much smaller than that of earlier raster graphics engines owing to the use of 1 bit logic rather than log2
Published in:
Electronics Letters
(Volume:24
,
Issue:
7
)
Date of Publication: 31 Mar 1988
- Page(s):
- 382 - 383
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 3151131
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- 31 Mar 1988
- Sponsored by :
- Institution of Engineering and Technology
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