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An analog-to-digital converter (ADC) is an essential device in mixed mode systems. The performance of the ADC, however, is deteriorated by coupled power supply noises through hierarchical chip-PCB power distributed networks (PDNs). In order to design a high-performance system, modeling and analysis of power supply noise effects on the ADC are necessary, as the power supply noise is coupled to the circuit through the hierarchical PDN structure in multilayer PCB substrates. In this paper, a hybrid model is proposed for analysis of power supply noise effects on the ADC. The model combines two modeling mechanisms. First, the coupling ratio of the power supply noise is derived by the combined model of hierarchical PDNs at the PCB and the chip. Second, an analytical model is proposed using equivalent circuits for analysis of the power supply noise effects on the ADC. The ADC is designed using a 0.13um CMOS process. The proposed model and analysis are verified based on a simulation from 100kHz to 4GHz. The performance of the ADC is dominantly affected by characteristics of the on-chip circuit under 100MHz. It is also confirmed that the Effective Number of Bits (ENOB) of the ADC is strongly dependent on the hierarchical PDN impedance over 100MHz. Furthermore, there are peak points caused by inter-modulation (IMD) and cavity resonances of PDN structures.