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Performance maximization of 3D-stacked cache memory on DVFS-enabled processor

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3 Author(s)
Kyungsu Kang ; Department of Electrical Engineering and Computer Science, Division of Electrical Engineering, KAIST, Daejeon, Republic of Korea ; Jongpil Jung ; Chong-Min Kyung

3D integration increases chip integration density, reduces wire length, wire delay and power consumption on wires. However, increased power density causes increase of temperature, which results in the increase of leakage power consumption and performance degradation. In this paper, we propose a solution to compromise these issues on stacking cache memory on a processor core. Experimental results have shown that the proposed method yields, on the average, 16% performance improvement in terms of instructions per second compared to conventional method. The proposed method also reduces energy consumption by 20% on average, in terms of energy per instruction.

Published in:

SoC Design Conference (ISOCC), 2010 International

Date of Conference:

22-23 Nov. 2010