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As the design for testability (DFT) is essential in the semiconductor manufacturing, the scan-based architecture is widely used to decrease the test complexity of a chip. However, the scan-based architecture requires high test cost such as the test data volume and the test time. In order to alleviate the test cost problem of the scan-based architecture, a lot of test data compression schemes using the scan slice encoding have been presented. In this paper, we propose a new scan slice encoding scheme with flexible code for test data compression. The proposed scheme fully utilizes the flexible code as the control code or the data code. The flexible code provides supplementary encoding mode without additional control code. As a result, the test cost is significantly reduced by the various encoding mode with low test equipment pin overhead. The experiment results based on ISCAS'89 benchmark circuits show that the test data volume and the test time is reduced up to 82% compared with the original data.