By Topic

Experimental via characterization for the signal integrity verification of discontinuous interconnect line

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hyewon Kim ; Electr. & Comput. Eng., Hanyang Univ., Ansan, South Korea ; Dongchul Kim ; Yungseon Eo

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process and measured using Vector Network Analyzer (VNA) up to 25 GHz. Then, by modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The circuit performance of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

Published in:

SoC Design Conference (ISOCC), 2010 International

Date of Conference:

22-23 Nov. 2010