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Enhenced redundancy analysis for memories using geometric faults based search tree

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3 Author(s)
Wooheon Kang ; Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea ; Hyungjun Cho ; Sungho Kang

With the growth of memory capacity and density, test cost and yield improvement are becoming more important. To increase yield of memory, redundancy analysis (RA) which analyzes the faults in memory is essential. However, the time for finding solutions to repair memories with faulty cells is very huge because most RA algorithms for automatic test equipment (ATE) are based on a tree structure. To reduce the time of memory test & repair is important to increase the memory yield using ATE. In order to reduce the time of memory test & repair, an RA algorithm with an early termination condition is proposed and it builds a geometric faults based search tree. To build the proposed algorithm, the faults in a memory are classified into geometric faults according to their characteristic. The experimental results show the effectiveness of the proposed algorithm.

Published in:

SoC Design Conference (ISOCC), 2010 International

Date of Conference:

22-23 Nov. 2010

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