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This work proposes a resource rebinding algorithm in high-level synthesis of 3D IC designs to improve timing under a floorplan information with thermal profile. Our proposed algorithm iteratively extracts a set of operations on critical timing path and updates their bindings to fine-tune the timing variation caused by the irregular temperature distribution. Precisely, the algorithm rebinds operations so that the temperature-induced timing variations should be as low as possible while considering TSV (Through-Silicon Via) cost. Through experimentations using MediaBench designs, it is shown that our thermal-aware rebinding algorithm is able to reduce the design latency by 15% ~ 20% further over the results by conventional thermal-unaware high-level synthesis.