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Increasing on-chip temperature in SoC designs has reinforced the need for Dynamic Thermal Management (DTM). The conventional DTM techniques adopted in microprocessors based on DVFS are not suitable in the context of SoCs as they tend to have multiple voltage and frequency domains. In this paper we propose a reactive and a predictive DTM technique using bus arbitration. Based on the thermal profile the bus grants and hence the bus transactions are controlled. This regulates the data flow which reduces the activity in the functional units. The results show that the on-chip temperature can be maintained 3-5°C below the chip temperature threshold with a worst case performance penalty of 5% and a fast response time of at most 5 clock cycles. The hardware cost of implementing the proposed scheme is 3619.7μm2 in 45 nm technology, which is less than 0.06% of the chip area. Apart from its simplicity, lower cost and effectiveness, the solution is non-intrusive on the design and scalable to many cores.