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An integrated patch-clamp amplifier for ultra-low current measurement on solid-state nanopore

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4 Author(s)
Jungsuk Kim ; Electr. Eng., Univ. of Santa Cruz, Santa Cruz, CA, USA ; Gang Wang ; Dunbar, W.B. ; Pedrotti, K.

In this paper, an integrated low-noise patch-clamp amplifier for a solid-state nanopore application is proposed which is composed of three stages: 1) a trans-impedance amplifier (TIA), 2) a voltage-gain amplifier (VGA), and 3) a unity-gain buffer. Because the first stage amplifier makes dominant impacts on gain, bandwidth, noise, stability, and area of the patch-clamp amplifier, in this work, we present the design analysis for the TIA and its optimal feedback resistance. The proposed patch-clamp amplifier has a maximum gain of 152.2dBΩ, an input-referred noise of 11.3pARMS within bandwidth of 10 KHz, and occupies an active die-area of 0.0625mm2. This amplifier is under fabrication in a 0.35μm CMOS 4M2P Process.

Published in:

SoC Design Conference (ISOCC), 2010 International

Date of Conference:

22-23 Nov. 2010