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Dynamic fault grouping for PROOFS: a win for large sequential circuits

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3 Author(s)
Graham, C.R. ; Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA ; Rudnick, E.M. ; Patel, J.H.

This paper discusses the important role of fault grouping in a parallel 32-bit fault simulator such as PROOFS. Three algorithms are presented which dynamically order the fault list during fault simulation to determine how the faults get grouped together. The dynamic fault grouping algorithms were incorporated into PROOFS and tested on benchmark circuits. The algorithms showed a marked reduction in the number of faulty circuit gate evaluations (compared to a static fault grouping) for almost all of the circuits with more than 20 flip-flops. For the largest benchmark circuit, s35932, all of the algorithms showed at least a 39% reduction in the number of faulty circuit gate evaluations and at least a 55% speedup in simulation time

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997