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On full reset as a design-for-testability technique

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2 Author(s)
Pomeranz, I. ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; Reddy, S.M.

Full scan design allows every combinationally irredundant fault in a synchronous sequential circuit to be tested. In this paper, we derive a similar result applicable to design-for-testability techniques that use reset instead of scan. We show that if reset states can be selected arbitrarily, a test sequence can be generated for every irredundant fault, i.e., for every fault which is not sequentially or combinationally redundant. Thus, increasing the circuit controllability is sufficient for detecting every irredundant fault, and improving its observability is not necessary for this purpose. We also show that of all the states of the circuit, it is sufficient to consider as possible reset states only the states extracted from a complete combinational test set. We describe two procedures to select the reset states and perform test generation for a given synchronous sequential circuit. Experimental results are given for ISCAS-89 benchmark circuits

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997