Cart (Loading....) | Create Account
Close category search window
 

FPGA implementation of median filter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Maheshwari, R. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India ; Rao, S.S.S.P. ; Poonacha, P.G.

This paper gives the algorithm and implementation details of a sliding real time 3×3 median filter. The design is implemented on a Xilinx XC4010 FPGA chip. It is tested and integrated at ER&DC, Trivandrum. The design is tailored to exploit certain features of sliding windows. The Algorithm used to implement median filter is very efficient and implementation results show the significant improvements in operating frequency and hardware requirements over general purpose techniques

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.