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FPGA implementation of median filter

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3 Author(s)
Maheshwari, R. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India ; Rao, S.S.S.P. ; Poonacha, P.G.

This paper gives the algorithm and implementation details of a sliding real time 3×3 median filter. The design is implemented on a Xilinx XC4010 FPGA chip. It is tested and integrated at ER&DC, Trivandrum. The design is tailored to exploit certain features of sliding windows. The Algorithm used to implement median filter is very efficient and implementation results show the significant improvements in operating frequency and hardware requirements over general purpose techniques

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997

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