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Adder and comparator synthesis with exclusive-OR transform of inputs

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3 Author(s)
J. Jacob ; Indian Inst. of Sci., Bangalore, India ; P. S. Sivakumar ; V. D. Agrawal

An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA for transformed functions is O(n2). In comparison, when the complete truth-table of an adder is minimized, the PLA size will be O(2n+2). Similarly, for an n bit comparator, the size of the PLA is reduced from O(2n+1 ) to O(n). These implementations require additional transform logic of complexity O(n), consisting of exclusive-OR gates

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997