VLSI implementation of modulo multiplication using carry free addition

In this paper we show how the technique of carry free addition can be used to get efficient algorithms for modulo multiplication. We present two algorithms and their VLSI implementations. The first algorithm runs in time O(nlogn) (for n bit numbers), has an AT/sup 2/ measure of O((nlogn)/sup 3/), and can be implemented using a systolic architecture. The second algorithm is a parallel modulo algorithm that uses table look up to speed up computation. The time complexity is O(logn), the AT/sup 2/ measure is O((n logn)/sup 2/), and it can also be implemented using a systolic architecture. Used with a O(logn) multiplier, it can perform module multiplication in O(logn) time. Both the algorithms have the advantage that the circuit is independent of the modulus N. Thus the same chip can be used for RSA cryptosystems with different moduli.