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Advances in optical networking technology are pushing internet link rates up to 100 Gbps. Such line rates demand a throughput of over 150 million packets per second at core routers. Along with the increase in link speed, the size of the dynamic routing table of these core routers is also increasing at the rate of 25-50 K additional prefixes per year. These dynamic tables require high prefix deletion and insertion rates. Therefore, rapid prefix update without disrupting router operation has also emerged as a critical requirement. Furthermore, IPv6 standard extends the current IPv4 prefix length from 32 to 128 bits. Thus, it is a major challenge to scale the existing solutions to simultaneously support increased throughput, table size, prefix length and rapid update. While the existing solutions can achieve high throughput, they cannot support large routing tables and rapid update at the same time. We propose a novel scalable, high-throughput linear pipeline architecture for IP-lookup that supports large routing tables and single-cycle non-blocking update. Using a state-of-the-art Field Programmable Gate Arrays (FPGA) along with external SRAM, the proposed architecture can support over 2M prefixes. Our implementation shows a throughput of 348 millions lookups per second, even when external SRAM is used.