An FPGA implementation of full-search variable block size motion estimation

In this paper, we propose an approach for full-search variable block size motion estimation using an FPGA. In the motion estimation, the current frame is divided to macro-blocks, and the best matching block is searched for each macroblock in the search area of the reference frame. In our approach, the scan direction of the macroblock in the current frame, and the scan direction of the matching in the search area are optimized in order to reduce the access to the off-chip memory banks which stores the reference frame, and the on-chip memory banks which cache the search area. By reducing both memory accesses, it becomes possible to realize high performance on a small size FPGA.