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Low power VLSI architectures for one bit transformation based fast motion estimation

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2 Author(s)
Chatterjee, S.K. ; Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India ; Chakrabarti, I.

In the present paper, architectures implementing fixed block size and variable block size (VBS) motion estimation (ME) algorithms on one bit transformed (1-BT) image frames have been presented. The proposed architectures perform ME by applying diamond search (DS) algorithm on 1-BT image frames. The 1-BT based ME is usually performed by applying full search (FS) algorithm. Our simulation results reveal that the application of DS on 1-BT based ME can significantly reduce the computational complexity which is observed in FS based 1-BT ME at a tolerable degradation in the quality. In terms of latency, the architectures have been shown to be superior to several other 1-BT ME architectures. The presented DS based 1-BT ME architectures have succeeded in reducing the minimum clock frequency required to process a video sequence with a given frame size and frame rate, which in turn reduces the overall power consumption compared with other ME architectures. In particular, for processing SDTV sequences (1280×720 @ 30 fps), the power consumption by the proposed VBS ME architecture is reduced by at least 41% compared to the other 1-BT based ME architectures available in literature. The proposed architectures are therefore, considered suitable for low-power portable video applications typically operated by battery power.

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:56 ,  Issue: 4 )

Date of Publication:

November 2010

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