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Asynchronous implementation of synchronous Esterel specifications

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3 Author(s)
R. S. Mitra ; Cadence Design Syst. Pvt. Ltd., Uttar Pradesh, India ; B. Bhattacharya ; L. Lavagno

The synchrony hypothesis of Esterel demands the generation of a single monolithic FSM from the specifications. However for large specifications, the size of this FSM can prove to be inhibitively large. In this paper, we propose a practical solution to this problem, which generates separate FSMs for each of the concurrent instructions. We also enumerate the deviations in semantics due to this translation algorithm so that the user is aware of the executable semantics that he should expect

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997