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A new methodology for the design of asynchronous digital circuits

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3 Author(s)
Nanda, K. ; Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, India ; Desai, S.K. ; Roy, S.K.

This paper discusses a new design methodology for asynchronous digital circuits. The methodology is based on an event driven scheme and follows the double-rail logic handshake protocol. A new logic gate, called the Universal Gate, is designed; this is the basic building block of the methodology. It is shown that the methodology, is completely delay insensitive. As an example, the Shift Multiplier is implemented

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997