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A dual-channel CMOS distributed amplifier (DA) is proposed for a highly linear receiver front-end. Proper choice for the number of stages and cutoff frequency of the distributed circuit realizes isolation between amplifier channels. Analysis of the distributed circuit describes the role of reverse gain in minimum noise figure (NF) and intermodulation distortion. The chip is fabricated in a 0.13-μm CMOS process, occupies an area of 0.60 mm2, and consumes 18 mW from a 1.2-V supply. Measurements of the DA show an NF of 5.7 dB, an output P1 dB of 4.9 dBm, and a forward gain of 9.6 dB at 24 GHz.