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Design for testability: today and in the future

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1 Author(s)
Williams, T.W. ; Technol. Products, IBM Corp., Boulder, CO, USA

Summary form only given. The author reviews the current techniques with a particular emphasis on today's Scan Designs. This entails distinguishing the differences between scan techniques, since all scans are not created equal! From this point the Testability Standards are discussed; these include the Boundary Scan activities and the Analog activities. Fault models are taking on more robust attributes, since the Stuck-At-Fault is necessary but not sufficient in today's technologies. The Delay Fault models are discussed with a comparison between a model which increases exponentially with gate count (Path Delay Fault) and one which increases linearly with gate count (Gate Delay Fault). Clearly, self-test is taking on an ever more important role which impacts both manufacturing testing and field system testing. The popular self-testing design techniques are shown. The interaction of testing and synthesis is discussed with a view on delay. Finally, the role of testing is explored in the new design environments which includes Hardware and Software Codesign

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997