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Optimizing test hardware for at-speed testing of datapaths in an integrated circuit

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3 Author(s)
D. Bhattacharya ; Texas Instrum. Inc., Dallas, TX, USA ; S. Freeman ; B. Lin

In this paper, we introduce a new representation method for datapath tests-called test template representation-and also introduce a new analysis technique to minimize the test logic overhead, through careful processing of the test templates. The resultant test structures represent the next systematic step beyond the multiplexer bypass method commonly found in commercial test tools

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997