A practical method for selecting partial scan flip-flops for large circuits

This paper describes a method of flip-flop selection (for BIST or Partial Scan) where the selection process proceeds in a module by module basis. A complete circuit is assumed to be made up of different modules. The method uses the circuit graph of an individual module and uses the top level connectivity information in between modules to select flip-flops in that module. It then deletes the module from the top level graph, keeping only the combinational paths through that module to select flip-flops in the next module and so on until all modules are exhausted. The advantage of this process lies in the fact that partial scan or BIST can be inserted in a circuit on a module by module basis which is how circuits are designed usually. This means that test logic insertion need not wait for the availability of the complete circuit. This can reduce the turnaround time of a design. Also the redesign time after test logic insertion will go down as the design optimization can be carried out with the test logic already inserted. A number of experiments were conducted using different circuits which showed that the percentage of extra flip-flops selected by this method as opposed to selection over the global circuit, was quite small (around 3%). Also the processing time went down as the number of flip-flops increased.