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A parallel architecture for video compression

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5 Author(s)
Bhattacharjee, S. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; Das, S. ; Saha, D. ; Roy Chowdhury, D.
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This paper reports a parallel algorithm for compression/decompression of video data files. The algorithm can be easily implemented on a parallel pipelined architecture that can support on-line compression/decompression. The hardware implementing the architecture achieves a throughput of 30 frames per second with frame size of 352×272 pixels

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997